1. Field of the Invention
The present invention generally relates to a multi-layer substrate and manufacture method thereof, and more particularly to a flat surface multi-layer substrate and manufacture method thereof.
2. Description of Prior Art
Miniaturization for electronic productions is an unavoidable trend in this modern world. While the scale of the semiconductor chips is continuously getting smaller, the scale of the related technology for packaging is also inevitably needed to be microminiaturized to follow the scale of the semiconductor chip. Today, because the integration of integrated circuits has been greatly increased, using a multi-layer substrate having high integration for packaging a chip device or an electronic component is necessary to obtain a high performance integration system consequently.
Please refer to FIG. 1, which illustrates a diagram of a multi-layer substrate according to prior art. The surface of the multi-layer substrate is the surface for connecting to a device or an electronic component. Such multi-layer substrate includes a bond pad layer 102, a surface dielectric layer 104 and a solder mask layer 106. The metal layer 108 under the bond pad layer 102 is electrically connected therewithin. According to prior arts, multiple metal layers (not shown) and multiple dielectric layers (not shown) are manufactured by Sequential Lamination method or by Build-up method, but in prior arts, the thickness of the surface dielectric layer 104 is larger then those of the bond pad layer 102 and the metal layer 108.
Generally, the thicknesses of the bond pad layer 102 and the metal layer 108 are only ranged from micrometers to dozens of micrometers, but the thickness of the surface dielectric layer 104 can greatly reach from dozens of micrometers up to 200 micrometers. As shown in FIG. 1, because the metal layer 108 exists under the bond pad layer 102, regardless of the manufacturing method by either the Sequential Lamination method or the Build-up method, the surface dielectric layer 104 having dielectric material layer of a certain thickness will make the bond pad layer on the surface of the multi-layer substrate not flat. As aforementioned, the surface dielectric layer 104 can be thickened up to 200 micrometers and the metal layer 108 is only ranged from micrometers to dozens of micrometers, that the thickness of the dielectric layer 104 is much thicker than that of the metal layer 108. Therefore, in the Sequential Lamination method or the Build-up method of prior arts, some process parameters in the methods may be adjusted to deform the surface dielectric layer 104 to make the flatness thereof into an acceptable range for the package.
However, with greater increase in the integration of integrated circuits, the smaller scale and the electrical performance of the semiconductor chips has to be re-considered. The thicknesses of the bond pad layer 102, the surface dielectric layer 104 and the metal layer 108 have to be smaller accordingly. Decreases of the thicknesses of the bond pad layer 102 and the metal layer 108 are limited for keeping the electrical performance of the transmission signals but decrease of the thickness of the surface dielectric layer 104 seems to be more practicable. PCB industry today has tried to manufacture a surface dielectric layer 104 which is only about ten micrometers. In a practical example, the thickness of the surface dielectric layer 104 comes to such scale of only ten micrometers and the thickness of the metal layer 108 may get smaller as a few micrometers or ten micrometers, whose scale of the thickness become in the same degree, the aforesaid means of deforming the surface dielectric layer 104 will fail to make the flatness thereof into an acceptable range for the package. The surface flatness of the multi-layer substrate inevitably becomes worse.
FIG. 2 illustrates a diagram of a multi-layer substrate connected to a chip device with a Flip-Chip package according to prior art. The multi-layer substrate manufacture of prior art has a dielectric layer 103, the corresponding metal layers 107-1, 107-2, the surface dielectric layer 104 and the corresponding metal layers 108-1, 108-2, 108-3 which are connected with bond pad layers 102-1, 102-2, 102-3 thereabove.
The Flip-Chip package shown in FIG. 2 is a common technique in the package technology today, such that Flip-Chip package is a skill to make the chip device face down to connect contacts 112-1, 112-2, 112-3 on the chip device surface with the bond pad layers 102-1, 102-2, 102-3 by metal bumps 120-1, 120-2, 120-3. The bond pad layers 102-1, 102-2, 102-3 have to connect and match with the contacts (electrodes) 112-1, 112-2, 112-3 precisely one to one. Therefore, in the Flip-Chip package, the multi-layer substrate is fixed in advance on a package tool for aligning the metal bumps 120-1, 120-2, 120-3 of the chip device with the bond pad layers 102-1, 102-2, 102-3 of the multi-layer substrate in precise respective positions. Thereafter, the Flip-Chip package is processed by hot pressing the contacts 112-1, 112-2, 112-3, and the bond pad layers 102-1, 102-2, 102-3, whose respective contacts will precisely connect thereto by respective metal bumps to complete the packaging.
However, because the design of the electric circuit of the multi-layer substrate, there may be metal layers 107-1, 107-2 under the metal layers 108-1, 108-3 but no corresponding metal layer under the metal layer 108-2. Therefore, the height of the bond pad layer 102-2 is lower than the height of the bond pad layers 102-1, 102-3. As the Flip-Chip package is processed, the metal bump 120-2 may fail to bond the bond pad layer 102-2 and the contact 112-2 of the chip device together.
Not only in the Flip-Chip package, but also in other high integration multi-contact package, such as, BGA package, LGA package, or CSP package, even one single metal bump fails to bond the bond pad, the whole package will fail. Therefore, the demand for the flatness and the coplanarity of the multi-layer substrate or the metal bump top is more than ever.
Generally, the tolerance of the metal bump can be about ±10 micrometers at 100 micrometers bond height and as aforementioned, with the greater increase of the integration of integrated circuits, the bump pitch also decreases. Furthermore, the bond height decreases accordingly at the same time, and aforesaid tolerance certainly becomes more critical. Consequently, the flatness of the multi-layer substrate surface (or the coplanarity of the bond pad layer and the surface dielectric layer) has to be more accurate. General thickness of the metal layer is about dozens of micrometers, even a few micrometers, and if the surface of the multi-layer substrate can not be flat enough, the yield and the reliability of the Flip-Chip package can be affected critically.
Therefore, a Flip-Chip package or other high integration multi-contact package can be benefited by a flat surface multi-layer substrate. A better package reliability can be obtained and bump height can be decreased further to increase the integration of the entire package.